In deep sub-micron integrated circuit technology, non-volatile memory device has become a popular storage unit due to various advantages. Particularly, the data saved in the non-volatile memory device are not lost when the power is turned off. One particular example of the non-volatile memory device includes a single floating gate to retain the electrical charges associated with the saved data. When complementary metal-oxide-semiconductor field effect transistor (CMOSFET) technology is implemented, salicide is formed on various contact regions, such as gate, source and drain, to reduce the contact resistance. When the integrated circuit including non-volatile memory device is scaled down through various technology nodes, the design of the memory device have a consideration of the process integration, such as alignment margin and other factors, leading to large memory cell size and low packing density. Therefore, a structure of the single non-volatile memory device and a method making the same are needed to address the above issue.